The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, during manufacturing, semiconductor device density varies across an IC device. This can cause issues during planarization processes, such as lateral etching issues in less dense areas of the IC device, and remaining material layers over semiconductor devices in more dense areas of the IC device. Although existing planarization methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.